Parallelism in a CRC Coprocessor

نویسنده

  • Andreas C. Döring
چکیده

Cyclic Redundancy Checks (CRC) constitute an important class of hash functions for detecting changes in data blocks after transmission, storage and retrieval, or distributed processing. Currently, most sequential methods based on Horner’s scheme are applied with some extensions or modifications. The flexibility of these methods with respect to the generator polynomial and the sequence of data processing is limited. A newly proposed algorithm and architecture [DW03, DW04] offer a high degree of flexibility in several aspects and provide high performance with a modest investment in hardware. The algorithm has inherent freedom for parallel processing on several levels, which is exploited in the proposed architecture. An early implementation gives quantitative results on cost and performance and suggests possible extensions and improvements. The algorithm, a typical system architecture, and the coprocessor’s structure are described in this paper with an emphasis on parallelism.

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Superscalar Coprocessor for High-Speed Curve-Based Cryptography

We propose a superscalar coprocessor for high-speed curvebased cryptography. It accelerates scalar multiplication by exploiting instruction-level parallelism (ILP) dynamically and processing multiple instructions in parallel. The system-level architecture is designed so that the coprocessor can fully utilize the superscalar feature. The implementation results show that scalar multiplication of ...

متن کامل

Versatile design of shared vector coprocessors for multicores

For most of the applications that make use of a vector coprocessor, its resources are not highly utilized due to the lack of sustained data parallelism, which often occurs due to insufficient vector parallelism or vector-length variations in dynamic environments. The motivation of our work stems from (a) the omnipresence of vector operations in high-performance scientific and emerging embedded ...

متن کامل

SIMD Implementation of a Multiplicative Schwarz Smoother for a Multigrid Poisson Solver on an Intel Xeon Phi Coprocessor

In this paper, we discuss an efficient implementation of the three-dimensional multigrid Poisson solver on a many-core coprocessor, Intel Xeon Phi. We have used the modified block red-black (mBRB) Gauss-Seidel (GS) smoother to achieve sufficient degree of parallelism and high cache hit ratio. We have vectorized (SIMDized) the GS steps in the smoother by introducing a partially SIMDizing techniq...

متن کامل

A Programmable Vector Coprocessor Architecture for Wireless Applications

The physical layers of most wireless protocols are traditionally implemented in ASICs due to the heavy computation requirements. These solutions are costly to design and hardwired solutions that offer no post-programmability. In this paper, we introduce a flexible coprocessor architecture customized for wireless protocols. To accomplish the design, a complete baseband physical layer for the 802...

متن کامل

Designing High-Performance Fuzzy Controllers Combining IP Cores and Soft Processors

This paper presents a methodology to integrate a fuzzy coprocessor described in VHDL (VHSIC Hardware Description Language) to a soft processor embedded into an FPGA, which increases the throughput of the whole system, since the controller uses parallelism at the circuitry level for high-speed-demanding applications, the rest of the application can be written in C/C++. We used the ARM 32-bit sof...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 2004